1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display device that is adaptive for preventing corrosion of a signal line.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal in accordance with video signals to display a picture corresponding to the video signals on a liquid crystal display panel. The liquid crystal display panel has liquid crystal cells arranged in a matrix.
The liquid crystal display device requires a plurality of integrated circuits (ICs) connected to data lines and gate lines to apply data signals and scanning signals to the data lines and the gate lines, respectively. Such ICs are provided between a printed circuit board (PCB) and the liquid crystal display panel to apply signals from the PCB to the data lines and the gate lines of the liquid crystal display panel. Different mounting methods of the ICs include a tape automated bonding (TAB) and a chip on glass (COG).
As shown in FIG. 1, a COG-type liquid crystal display device includes a picture display part 14 at which the liquid crystal cells are positioned, first and second gate shorting bars 2a and 2b for testing gate lines 20 of the picture display part 14, and first and second data shorting bars 4a and 4b for testing data lines 22 of the picture display part 14.
The picture display part 14 displays a picture corresponding to video signals such as television signals on a pixel matrix in which pixels are arranged at each intersection between the gate lines 20 and the data lines 22. Each pixel is comprised of a liquid crystal cell 12 for controlling the amount of transmitted light in accordance with a voltage level of a data signal of the data line 22, and a thin film transistor 10 for responding to a scanning signal from the gate line 20 to switch a data signal transferred from the data line 22 into the liquid crystal cell 12. The left side of the picture display part 14 is provided with a gate pad area 18 for mounting a gate driving IC (not shown) while the upper side of the picture display part 14 is provided with a data pad area 16 for mounting a data driving IC (not shown).
The first and second gate shorting bars 2a and 2b are provided at the right side of the picture display part 14 because the gate driving IC is mounted onto the gate pad area 18. The first gate shorting bar 2a is formed from a gate metal layer to be directly connected to the odd-numbered gate lines 20 as shown in FIG. 2 and FIG. 3. The second gate shorting bar 2b is formed from a data metal layer, and a gate test electrode 6 extended from the second gate shorting bar 2b is connected, via transparent metal pattern 24, to the even-numbered gate lines 20. The gate test electrode 6 is connected, via a first gate contact hole 26a passing through a protective layer 34, to the transparent metal pattern 24, which is connected, via a second contact hole 26b passing through the protective layer 34 and the gate insulating film 32, to the gate line 20.
The first and second data shorting bars 4a and 4b are provided at the lower side of the picture display part 14 because the data driving IC is mounted onto the data pad area 16. The first data shorting bar 4a is connected, via a data test electrode 8 formed from a gate metal layer, to the odd-numbered data lines 22 as shown in FIG. 4 and FIG. 5. The data test electrode 8 is connected, via a first data contact hole 30a passing through the gate insulating film 32 and the protective layer 34, to the transparent metal pattern 28, which is connected, via a second data contact hole 30b passing through the protective film 34, to the odd-numbered data lines 22. The second data shorting bar 4b is formed from a data metal layer and is directly connected to the even-numbered data lines 22.
The TFT's and the liquid crystal cells provided at the picture display part 14 are tested with the aid of a test signal applied to the gate shorting bars 2a and 2b and the data shorting bars 4a and 4b. 
A test process of the gate line will be briefly described below.
First, a voltage level corresponding to a data signal is applied to the data lines 22. At the same time, a voltage level corresponding to a scanning signal is sequentially applied to the first gate shorting bar 2a connected to the odd-numbered gate lines GL1, GL3, GL5, . . . , GLm of the gate lines 20 and the second gate shorting bar 2b connected to the even-numbered gate lines GL2, GL4, GL6, . . . , GL(m-1) thereof.
The TFT's 10 connected to the odd-numbered gate lines GL1, GL3, . . . , GLm is turned on by the scanning signal applied to the first gate shorting bar 2a and, at the same time, a data signal applied to the data lines DL1 to DLn is transferred to the liquid crystal cells 12, thereby driving the liquid crystal cells 12. Likewise, the liquid crystal cells 12 connected to the even-numbered gate lines GL2, GL4, . . . , GL(m-1) are driven with the scanning signal applied to the second gate shorting bar 2b. Herein, if any ones of the gate lines GL and the data lines DL are short-circuited and opened, then the liquid crystal cells 12 corresponding to these lines fail to be driven.
By such a strategy, defects causing short or open circuits of the gate line and the data line and defects of the TFT occurring at the picture display part 14 can be tested. After this test process, if the TFT's and the signal lines have no defects, then the lower substrate 1 is taken along a cutting line SCL and the upper substrate is disposed on the cut lower substrate 1.
However, when the lower substrate 1 of the conventional liquid crystal display device is taken along the cutting line SCL, the data lines 22 and the gate lines 20 are exposed in the side direction. The exposed gate line 22 and data lines 20 and 22 are liable to be corroded in a high temperature and humidity environment or in a state that are supplied with an electric field upon driving of the TFT's. Such corrosion is propagated into the gate lines 20 and the data lines 22, and furthermore may be progressed into the TFT's with the lapse of time.